The present invention relates to architectures for integrated circuits and in particular to a method and apparatus for managing transistor leakage currents in high-density integrated circuits such as microprocessors and the like.
Managing the power consumption of integrated circuits such as microprocessors is important for the purposes of energy conservation, providing improved battery life for portable devices, and reducing problems of device cooling.
One method of reducing power consumption is to place the integrated circuit in a “sleep state” when its full capabilities are not required. The sleep state may be implemented through a set of power gating transistors placed between the input power terminal (VDD) of the integrated circuit and an effective power terminal (VVDD) of the of the integrated circuitry that will be shut down to conserve power. A sleep/wake signal (generated externally or internally) turns these power gating transistors off or on.
Normally, the power gating transistors are implemented as multiple transistors connected in parallel in order to provide sufficient current flow for the anticipated maximum current consumption of the integrated circuit with a low voltage drop.